This application claims the benefit of a Japanese Patent Application No. 2002-190556 filed Jun. 28, 2002, in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to instruction control methods and processors, and more particularly to an instruction control method for processing a plurality of instructions including branch instructions at a high speed in an instruction control which involves branch prediction and delay instructions for branching, and to a processor which employs such an instruction control method.
2. Description of the Related Art
Recently, various instruction processing methods are employed in order to improve the performance of the processor. An out-of-order processing method is one of such instruction processing methods. In the processor which employs the out-of-order processing method, a completion of one instruction execution is not waited and subsequent instructions are successively inserted into a plurality of pipelines to execute the instructions, so as to improve the performance of the processor.
However, in a case where execution of a preceding instruction affects execution of a subsequent instruction, the subsequent instruction cannot be executed unless the execution of the preceding instruction us completed. If the processing of the preceding instruction which affects the execution of the subsequent instruction is slow, the subsequent instruction cannot be executed during the processing of the preceding instruction, and the subsequent instruction must wait for the completion of the execution of the preceding instruction. As a result, the pipeline is disturbed, and the performance of the processor deteriorates. Such a disturbance in the pipeline is particularly notable in the case of a branch instruction.
The branch instructions include conditional branch instructions. In the case of the conditional branch instruction, if an instruction exists which changes the branch condition (normally, a condition code) immediately prior to the conditional branch instruction, the branch does not become definite until this instruction is completed. Accordingly, because the sequence subsequent to the branch instruction is unknown, the subsequent instructions cannot be executed, and the process stops to thereby deteriorate the processing capability. This phenomenon is not limited to the processor employing the out-of-order processing method, and a similar phenomenon occurs in the case of processors employing processing methods such as a lock step pipeline processing method. However, the performance deterioration is particularly notable in the case of the processor employing the out-of-order processing method. Hence, in order to suppress the performance deterioration caused by the branch instruction, a branch prediction mechanism is normally provided in an instruction control unit within the processor. The branch prediction mechanism predicts the branching, so as to execute the branch instruction at a high speed.
When using the branch prediction mechanism, the subsequent instruction and the instruction at the branching destination are executed in advance, before judging whether or not a branch occurs when executing the branch instruction. If the branching occurs as a result of executing the branch instruction, the branch prediction mechanism registers therein a pair of instruction address at the branching destination and an instruction address of the branch instruction itself. When the instruction is read from a main storage within the processor in order to execute the instruction, the registered instruction addresses registered within the branch prediction mechanism are searched prior to executing the instruction. By providing the branch prediction mechanism and predicting the branching, the instruction control unit can fetch the instructions from the main storage and successively execute the instructions while minimizing delay of the instructions.
A problem occurs when an instruction control method which is employed by the processor uses delay instructions for branching. In this case, the branch instruction is executed in the following manner. For example, if an instruction sequence is a1, a2, a3, a4, a5, a6, a3 is a conditional branch instruction and a4 is a delay instruction, the instructions are executed in a sequence a1, a2, a3, a4, b1, b2 if the conditional branch instruction a3 branches, and are executed in a sequence a1, a2, a3, a5, a6 if the conditional branch instruction a3 does not branch, where b1 is an instruction at the branching destination.
According to the prior art, branch information indicating whether or not a branch instruction at an arbitrary instruction address has branched in the past is registered, and the instruction address of the branch instruction, the instruction address at the branching destination when branching or the instruction address which is executed next when not branching are paired with the branch information and registered therewith. The registered branch information and instruction. address pair is used to predict whether or not the branch instruction branches. However, in either case where the branch instruction branches and the branch instruction does not branch, the pair of branch information and instruction address must be registered, and there was a problem in that a large storage capacity is required for the instruction control.
In addition, when the prediction of the branching fails, and particularly when the branch instruction which could not be predicted is decoded, it is always necessary to temporarily stop executing the subsequent instructions until the branch condition of the branch instruction becomes definite and the judgement is made on the branch, regardless of whether or not the branch instruction branches. As a result, the entire process flow of the instruction process within the processor is stopped temporarily, and there was a problem in that the performance of the processor greatly deteriorates.